Welcome to OpenFPGA’s documentation!¶
- OpenFPGA Flow
- OpenFPGA Architecture Description
- OpenFPGA Shell
- FPGA-SPICE
- FPGA-Verilog
- FPGA-Bitstream
- File Formats
- Pin Constraints File (.xml)
- Repack Design Constraints (.xml)
- Architecture Bitstream (.xml)
- Fabric-dependent Bitstream
- Bitstream Setting (.xml)
- Fabric Key (.xml)
- I/O Mapping File (.xml)
- I/O Information File (.xml)
- Bitstream Distribution File (.xml)
- Bus Group File (.xml)
- Pin Constraints File (.pcf)
- Pin Table File (.csv)
- Contact
- Publications & References
- Frequently Asked Questions
- Where is the best place to get help with OpenFPGA?
- What should I do if check-in tests failed when first installing OpenFPGA?
- How to sweep design parameters in a task run of OpenFPGA design flow?
- How do I setup OpenFPGA to be used by multiple users on a single device?
- How do I contribute to OpenFPGA?
For more information on the VTR see vtr_doc or vtr_github
For more information on the Yosys see yosys_doc or yosys_github
For more information on the original FPGA architecture description language see xml_vtr